I. Field of the Disclosure
The technology of the disclosure relates generally to translation caches provided by memory management units (MMUs).
II. Background
Virtual memory is a memory management technique provided by most modern computing systems. Using virtual memory, a central processing unit (CPU) or a peripheral device of the computing system may access a memory buffer using a virtual memory address mapped to a physical memory address within a physical memory space. In this manner, the CPU or peripheral device may be able to address a larger physical address space than would otherwise be possible, and/or may utilize a contiguous view of a memory buffer that is, in fact, physically discontiguous across the physical memory space.
Virtual memory is conventionally implemented through the use of a memory management unit (MMU) for translation of virtual memory addresses to physical memory addresses. The MMU may be integrated into the CPU of the computing system (a CPU MMU), or may comprise a separate circuit providing memory management functions for peripheral devices (a system MMU, or SMMU). In conventional operation, the MMU receives memory access requests from “upstream” devices, such as direct memory access (DMA) agents, video accelerators, and/or display engines, as non-limiting examples. For each memory access request, the MMU translates the virtual memory addresses included in the memory access request to a physical memory address, and the memory access request is then processed using the translated physical memory address.
Because an MMU may be required to translate a same virtual memory address repeatedly within a short time interval, performance of the MMU and the computing system overall may be improved by caching address translation data within the MMU. In this regard, the MMU may include a structure known as a translation cache (also referred to as a translation lookaside buffer, or TLB). The translation cache provides translation cache entries in which previously generated virtual-to-physical memory address translation mappings may be stored for later access. If the MMU subsequently receives a request to translate a virtual memory address stored in the translation cache, the MMU may retrieve the corresponding physical memory address from the translation cache rather than retranslating the virtual memory address.
However, the performance benefits achieved through use of the translation cache may be lost in scenarios in which the MMU provides address translation services for multiple upstream devices. Because the upstream devices must share the resources of the MMU's translation cache, competition for the limited number of translation cache entries may result in “thrashing,” in which two or more upstream devices repeatedly evict each other's translation cache entries in favor of their own. In a worst-case scenario, the additional overhead resulting from thrashing may cancel out the benefits of caching. A larger translation cache may mitigate the effects of inter-device competition for translation cache entries, but may also result in increased power consumption and a larger physical footprint.